The present invention relates to non-volatile memory cells using ferroelectric capacitors. A ferroelectric capacitor is described generally in Rohrer U.S. Pat. No. 3,728,694. It shows a hysteresis curve for a ferroelectric material plotting polarization against applied field. As described in the '694 patent and in the currently pending patent application of my colleague, S. Sheffield Eaton, Jr., U.S. Ser. No. 013,746 entitled "Self-Restoring Ferroelectric Memory," filed Feb. 12, 1987, the entire disclosure of which is incorporated herein by reference, non-volatile memories can be designed which use the polarization state of the ferroelectric material as the physical phenomenon or property by which binary data can be stored. A memory cell may consist of simply a capacitor of the ferroelectric type having two plate electrodes, which may be coupled to respective row and column lines, as illustrated as prior art in FIG. 2 of the Eaton '746 application. That arrangement, unfortunately, has not been successful because the application of the signal to read one such capacitor in a matrix of many resulted in disturbing other capacitors along the same row and/or column.
Accordingly, better memory cells which use ferroelectric capacitors have been desired for many years, and some memory cells are illustrated in the Eaton '746 application. In FIG. 3 thereof, a one transistor-one capacitor memory cell is illustrated. Briefly, the ferroelectric capacitor has two plate electrodes, one of which is coupled to a conductor which may be referred to as a "plate line." The other electrode of the capacitor is coupled via a switching device such as the source-drain path of as a field effect transistor to a bit line. Such a transistor is controlled by a word line coupled to the gate electrode of the transistor. Further shown in FIG. 3 of that Eaton application is a sense amplifier and a dummy cell of similar configuration, although the capacitance of the ferroelectric capacitor in the dummy cell may be different than that of the capacitor in the operative cell. That configuration permitted a new type of operation concerning reading the polarization state of the ferroelectric capacitor.
The '746 Eaton application also disclosed in FIG. 4 and FIG. 6 a two transistor, two capacitor memory cell wherein a sense amplifier was connected to complementary bit lines. As in the Eaton FIG. 3 embodiment described above, each of the two capacitors is coupled by the source-drain path of a respective field effect transistor to a respective bit line. Both transistors are gated by a word line, and the other plates of the capacitors are both coupled to a plate line which can run parallel to the word line, as shown in FIGS. 4 and 5, or which can be perpendicular to the word line, as shown in FIG. 6. Thus, by combining a ferroelectric capacitor with a transistor to provide access to the capacitor, Eaton was able to provide a measure of isolation to the capacitors which were not being selected for reading in a matrix of memory cells.
The present invention provides further isolation for ferroelectric capacitors. The invention also provides a new manner of reading the polarization state of a ferroelectric capacitor.